1. Field
Various exemplary embodiments of the present invention relate to a semiconductor memory system, and more particularly, to a semiconductor memory system and an operating method thereof capable of improving reliability of data read.
2. Description of the Related Art
A nonvolatile semiconductor memory device such as a flash memory device retains data stored in a memory block despite of power cut-off. The nonvolatile semiconductor memory device can repeatedly store data into the memory block by repeatedly performing operations of programming and erasing data. The number of program/erase cycles represents the number of repetitions of such program operations and erase operations. A single program/erase cycle comprises a single program operation and a single erase operation. As the program operations and the erase operations are repeatedly performed, the number of program/erase cycles may increase.
The numbers of program/erase cycles may be divided into a plurality of program/erase cycle groups with reference to a program voltage. Also, the number of program/erase cycles may be divided into a plurality of read-retry groups with reference to a read voltage.
FIG. 1A is a table illustrating the program/erase cycle groups applicable to data program in a semiconductor memory device. FIG. 1B is a table illustrating the read-retry groups applicable to data read in a semiconductor memory device.
Referring to FIG. 1A, the program/erase cycle groups may comprise first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr5. For example, the first program/erase cycle group PGr1 may represent the number of program/erase cycles ranging over 0 and under 0.2K, the second program/erase cycle group PGr2 may represent the number of program/erase cycles ranging over 0.2K and under 0.5K the third program/erase cycle group PGr3 may represent the number of program/erase cycles ranging over 0.5K and under 1K, the fourth program/erase cycle group PGr4 may represent the number of program/erase cycles ranging over 1K and under 2K, and the fifth program/erase cycle group PGr5 may represent the number of program/erase cycles ranging over 2K and under 3K.
Each of the first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr5 includes a plurality of indexes representing addresses of the memory block. The plurality of indexes may correspond to the plurality of program voltages PVL, respectively. For example, Index 0 to Index n of the first program/erase cycle group PGr1 may correspond to values of the program voltages PV10 to PV1n applied to the 0th to nth memory blocks, respectively, during the data programming. Index 0 to Index n of the second program/erase cycle group PGr2 may correspond to values of the program voltages PV20 to PV2n applied during the data programming. Index 0 to Index n of the third program/erase cycle group PGr3 may correspond to values of the program voltages PV30 to PV3n applied during the data programming. Index 0 to Index n of the fourth program/erase cycle group PGr4 may correspond to values of the program voltages PV40 to PV4n applied during the data programming. Index 0 to Index n of the fifth program/erase cycle group PGr5 may correspond to values of the program voltages PV50 to PV5n applied during the data programming.
Referring to FIG. 1B, the read-retry groups may comprise first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4 and RGr5. The first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4 and RGr5 corresponds to first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr5, respectively.
For example, the first read-retry group RGr1 may represent the number of program/erase cycles ranging over 0 and under 0.2K, the second read-retry group RGr2 may represent the number of program/erase cycles ranging over 0.2K and under MK, the third read-retry group RGr3 may represent the number of program/erase cycles ranging over 0.5K and under 1K, the fourth read-retry group RGr4 may represent the number of program/erase cycles ranging over 1K and under 2K, and the fifth read-retry group RGr5 may represent the number of program/erase cycles ranging over 2K and under 3K.
Each of the first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4 and RGr5 includes Index 0 to Index n, respectively. Each of Index 0 to Index n may correspond to values of plural read voltages applied to the 0th to nth memory blocks, respectively, during data read of multi-level cell (MLC) flash memory device. For example, the 0th index (Index 0) may correspond to 3 values RV10, RV20 and RV30 of the read voltages REVL1, REVL2, and REVL3 applied to the 0th memory block during the data read of MLC. The first index (Index 1) may correspond to 3 values RV11, RV21 and RV31 of the read voltages REVL1, REVL2, and REVL3 applied to the first memory block during the data read of MLC. The nth index (Index n) may correspond to 3 values RV1n, RV2n and RV3n of the read voltages REVL1, REVL2, and REVL3 applied to the nth memory block during the data read of MLC.
The plural program/erase cycle groups and the plural read-retry groups may be managed by unit of a memory chip.
When data is programmed into a semiconductor memory device using the first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr5, and then the data is read from the semiconductor memory device using the first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4 and RGr5, a mismatch may occur.
For example, the data program operation is performed to the first memory block in a memory chip using the second program/erase cycle group PGr2 when the number of program/erase cycles of the memory chip is 499. After that, the data program operation is performed to the third memory block of the same memory chip using the third program/erase cycle group PGr3 when the number of program/erase cycles of the memory chip is changed to 501 due to further program operation to the same memory chip. That is, the data program operation is performed to the first and third memory blocks of the same memory chip using the second and the third program/erase cycle groups PGr2 and PGr3 which are different from each other, according to the number of program/erase cycles.
After that, during the data read operation to the first memory block, data is read from the first memory block with reference to the third read-retry group RGr3 when the number of program/erase cycles of the memory chip is under 999.
Read fail of the first memory block may occur because data is programmed to the first memory block using the second program/erase cycle group PGr2 and the programmed data is read from the first memory block with reference to the third read-retry group RGr3, That is, the read fail of the first memory block may occur because of the difference between the program condition and the read condition.
As described above, the read fail may occur when the program condition and the read condition are different from each other. Therefore, stable operation of the semiconductor memory device may not be performed, deteriorating the characteristic of the semiconductor memory device.